jurjen.ladeniusandClaude Opus 4.8
f3340e86c6
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
195 lines
6.8 KiB
C
195 lines
6.8 KiB
C
/*-------------------------------------------------------------------------
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ds80c390.h - Register Declarations for the DALLAS DS80C390 Processor
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far from complete, e.g. no CAN
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Copyright (C) 2000, Johan Knol <johan.knol AT iduna.nl>
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This library is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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Free Software Foundation; either version 2, or (at your option) any
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later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this library; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
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MA 02110-1301, USA.
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As a special exception, if you link this library with other files,
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some of which are compiled with SDCC, to produce an executable,
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this library does not by itself cause the resulting executable to
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be covered by the GNU General Public License. This exception does
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not however invalidate any other reasons why the executable file
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might be covered by the GNU General Public License.
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-------------------------------------------------------------------------*/
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#ifndef DS80C390_H
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#define DS80C390_H
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__sfr __at 0x80 P4; /* ce3..ce0, a19..a16 */
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__sfr __at 0x81 SP; /* stack pointer */
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__sfr __at 0x82 DPL; /* data pointer 0 lsb */
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__sfr __at 0x83 DPH; /* data pointer 0 msb */
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__sfr __at 0x84 DPL1; /* data pointer 1 lsb */
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__sfr __at 0x85 DPH1; /* data pointer 1 msb */
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__sfr __at 0x86 DPS; /* data pointer select */
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__sfr __at 0x87 PCON; /* power control */
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__sfr __at 0x88 TCON; /* timer/counter control */
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__sbit __at 0x88 IT0;
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__sbit __at 0x89 IE0;
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__sbit __at 0x8a IT1;
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__sbit __at 0x8b IE1;
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__sbit __at 0x8c TR0;
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__sbit __at 0x8d TF0;
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__sbit __at 0x8e TR1;
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__sbit __at 0x8f TF1;
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__sfr __at 0x89 TMOD; /* timer mode control */
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__sfr __at 0x8a TL0; /* timer 0 lsb */
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__sfr __at 0x8b TL1; /* timer 1 msb */
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__sfr __at 0x8c TH0; /* timer 0 msb */
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__sfr __at 0x8d TH1; /* timer 1 msb */
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__sfr __at 0x8e CKCON; /* clock control */
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__sfr __at 0x90 P1;
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__sbit __at 0x90 T2;
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__sbit __at 0x91 T2EX;
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__sbit __at 0x92 RXD1;
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__sbit __at 0x93 TXD1;
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__sbit __at 0x94 INT2;
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__sbit __at 0x95 INT3;
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__sbit __at 0x96 INT4;
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__sbit __at 0x97 INT5;
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__sfr __at 0x91 EXIF; /* external interrupt flag */
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__sfr __at 0x92 P4CNT;
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__sfr __at 0x93 DPX; /* extended datapointer 0 */
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__sfr __at 0x95 DPX1; /* extended datapointer 1 */
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__sfr __at 0x98 SCON0; /* serial 0 control */
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__sbit __at 0x98 RI_0;
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__sbit __at 0x99 TI_0;
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__sbit __at 0x9a RB8_0;
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__sbit __at 0x9b TB8_0;
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__sbit __at 0x9c REN_0;
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__sbit __at 0x9d SM2_0;
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__sbit __at 0x9e SM1_0;
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__sbit __at 0x9f SM0_0;
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__sbit __at 0x9f FE_0; /* depending on SMOD0 */
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__sfr __at 0x99 SBUF0; /* serial 0 data buffer */
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__sfr __at 0x9b ESP; /* extended stack pointer */
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__sfr __at 0x9c AP; /* address page */
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__sfr __at 0x9d ACON; /* address control */
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__sfr __at 0xa0 P2; /* never mind the sbits */
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__sfr __at 0xa1 P5;
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__sfr __at 0xa2 P5CNT;
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__sfr __at 0xa8 IE; /* interrupt enable */
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__sbit __at 0xa8 EX0;
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__sbit __at 0xa9 ET0;
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__sbit __at 0xaa EX1;
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__sbit __at 0xab ET1;
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__sbit __at 0xac ES0;
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__sbit __at 0xad ET2;
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__sbit __at 0xae ES1;
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__sbit __at 0xaf EA;
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__sfr __at 0xb0 P3;
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__sbit __at 0xb0 RXD0;
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__sbit __at 0xb1 TXD0;
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__sbit __at 0xb2 INT0;
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__sbit __at 0xb3 INT1;
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__sbit __at 0xb4 T0;
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__sbit __at 0xb5 T1;
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__sbit __at 0xb6 WR;
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__sbit __at 0xb7 RD;
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__sfr __at 0xb8 IP; /* interupt priority */
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__sbit __at 0xb8 PX0; /* external 0 */
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__sbit __at 0xb9 PT0; /* timer 0 */
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__sbit __at 0xba PX1; /* external 1 */
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__sbit __at 0xbb PT1; /* timer 1 */
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__sbit __at 0xbc PS0; /* serial port 0 */
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__sbit __at 0xbd PT2; /* timer 2 */
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__sbit __at 0xbe PS1; /* serial port 1 */
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__sfr __at 0xc0 SCON1; /* serial 1 control */
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__sbit __at 0xc0 RI_1;
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__sbit __at 0xc1 TI_1;
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__sbit __at 0xc2 RB8_1;
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__sbit __at 0xc3 TB8_1;
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__sbit __at 0xc4 REN_1;
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__sbit __at 0xc5 SM2_1;
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__sbit __at 0xc6 SM1_1;
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__sbit __at 0xc7 SM0_1;
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__sbit __at 0xc7 FE_1; /* depending on SMOD0 */
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__sfr __at 0xc1 SBUF1; /* serial 1 data buffer */
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__sfr __at 0xc4 PMR; /* power managment */
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__sfr __at 0xc6 MCON; /* memory control register */
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__sfr __at 0xc7 TA; /* timed access register */
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__sfr __at 0xc8 T2CON; /* timer 2 control */
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__sbit __at 0xc8 CP_RL; /* capture/reload */
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__sbit __at 0xc9 C_T; /* count/timer */
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__sbit __at 0xca TR2; /* stop/run */
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__sbit __at 0xcb EXEN2;
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__sbit __at 0xcc TCLK;
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__sbit __at 0xcd RCLK;
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__sbit __at 0xce EXF2;
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__sbit __at 0xcf TF2; /* overflow flag */
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__sfr __at 0xc9 T2MOD; /* timer 2 mode */
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__sfr __at 0xca RCAP2L; /* timer 2 capture/reload */
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__sfr __at 0xca RTL2; /* depends on CP_RL */
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__sfr __at 0xcb RCAP2H;
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__sfr __at 0xcb RTH2;
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__sfr __at 0xcc TL2; /* timer 2 lsb */
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__sfr __at 0xcd TH2; /* timer 2 msb */
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__sfr __at 0xd0 PSW; /* program status word (byte actually) */
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__sbit __at 0xd0 P; /* parity */
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__sbit __at 0xd1 F1; /* user flag 1 */
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__sbit __at 0xd2 OV; /* overflow flag */
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__sbit __at 0xd3 RS0; /* register select l */
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__sbit __at 0xd4 RS1; /* register select h */
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__sbit __at 0xd5 F0; /* user flag 0 */
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__sbit __at 0xd6 AC; /* auxiliary carry flag */
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__sbit __at 0xd7 CY; /* carry flag */
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__sfr __at 0xd1 MCNT0; /* arithmetic accellerator */
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__sfr __at 0xd2 MCNT1;
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__sfr __at 0xd3 MA;
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__sfr __at 0xd4 MB;
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__sfr __at 0xd5 MC;
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__sfr __at 0xd8 WDCON; /* watch dog */
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__sbit __at 0xd8 RWT;
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__sbit __at 0xd9 EWT;
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__sbit __at 0xda WDRF;
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__sbit __at 0xdb WDIF;
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__sbit __at 0xdc PFI;
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__sbit __at 0xdd EPFI;
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__sbit __at 0xde POR;
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__sbit __at 0xdf SMOD_1;
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__sfr __at 0xe0 ACC; /* accumulator */
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__sfr __at 0xe8 EIE; /* extended interrupt enable */
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__sbit __at 0xe8 EX2;
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__sbit __at 0xe9 EX3;
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__sbit __at 0xea EX4;
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__sbit __at 0xeb EX5;
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__sbit __at 0xec EWDI;
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__sbit __at 0xed C1IE;
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__sbit __at 0xee C0IE;
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__sbit __at 0xef CANBIE;
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__sfr __at 0xea MXAX; /* extended address register */
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__sfr __at 0xf0 B; /* aux accumulator */
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__sfr __at 0xf8 EIP; /* extended interrupt priority */
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__sbit __at 0xf8 PX2;
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__sbit __at 0xf9 PX3;
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__sbit __at 0xfa PX4;
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__sbit __at 0xfb PX5;
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__sbit __at 0xfc PWDI;
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__sbit __at 0xfd C1IP;
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__sbit __at 0xfe C0IP;
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__sbit __at 0xff CANBIP;
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/* WORD/DWORD Registers */
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__sfr16 __at (0x8C8A) TMR0; /* TIMER 0 COUNTER */
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__sfr16 __at (0x8D8B) TMR1; /* TIMER 1 COUNTER */
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__sfr16 __at (0xCDCC) TMR2; /* TIMER 2 COUNTER */
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__sfr16 __at (0xCBCA) RCAP2; /* TIMER 2 CAPTURE REGISTER WORD */
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#endif /* DS80C390_H */
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