Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
150 lines
3.9 KiB
C
150 lines
3.9 KiB
C
//_____________________________________________________________________________
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// ▄▄ ▄ ▄ ▄▄▄ ▄▄ ▄ ▄
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// ██ ▀ ██▀█ ▀█▄ ▀█▄▀ ▀▀██ ▄ ██▀▄
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// ▀█▄▀ ██ █ ▄▄█▀ ██ █ ██▄▄ ██ ██▀
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//______________________________▀▀ ___________________________________________
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//
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// by Guillaume "Aoineko" Blanchard (aoineko@free.fr)
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// available on GitHub (https://github.com/aoineko-fr/MSXbin)
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// under CC-BY-AS free license (https://creativecommons.org/licenses/by-sa/2.0/)
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//_____________________________________________________________________________
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#pragma once
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// MSXtk
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#include "MSXtk.h"
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//=============================================================================
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// DEFINES
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//=============================================================================
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#define VGM_IDENT *(u32*)"Vgm "
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#define VGM_WAIT_60HZ 735 // 60 Hz
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#define VGM_WAIT_50HZ 882 // 50 Hz
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// VGM commands
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enum VGM_COMMAND
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{
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// Chips
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VGM_CMD_AY8910 = 0xA0, // aa dd | PSG/AY8910, write value dd to register aa
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VGM_CMD_YM2413 = 0x51, // aa dd | MSX-MUSIC/YM2413/OPLL, write value dd to register aa
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VGM_CMD_Y8950 = 0x5C, // aa dd | MSX-AUDIO/Y8950/OPL1, write value dd to register aa
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VGM_CMD_SCC = 0xD2, // pp aa dd | SCC/SCC+/K051649/K052539, port pp, write value dd to register aa
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VGM_CMD_YMF278 = 0xD0, // pp aa dd | MOONSOUND/YMF278B/OPL4, port pp, write value dd to register aa
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// Waits
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VGM_CMD_WAIT_16B = 0x61, // nn nn | Wait n samples, n can range from 0 to 65535 (approx 1.49 seconds).Longer pauses than this are represented by multiple wait commands.
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VGM_CMD_WAIT_60HZ = 0x62, // wait 735 samples(60th of a second), a shortcut for 0x61 0xdf 0x02
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VGM_CMD_WAIT_50HZ = 0x63, // wait 882 samples(50th of a second), a shortcut for 0x61 0x72 0x03
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VGM_CMD_WAIT_4B = 0x7F, // wait n+1 samples, n can range from 0 to 15.
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VGM_CMD_WAIT_1 = 0x70,
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VGM_CMD_WAIT_2 = 0x71,
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VGM_CMD_WAIT_3 = 0x72,
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VGM_CMD_WAIT_4 = 0x73,
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VGM_CMD_WAIT_5 = 0x74,
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VGM_CMD_WAIT_6 = 0x75,
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VGM_CMD_WAIT_7 = 0x76,
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VGM_CMD_WAIT_8 = 0x77,
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VGM_CMD_WAIT_9 = 0x78,
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VGM_CMD_WAIT_10 = 0x79,
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VGM_CMD_WAIT_11 = 0x7A,
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VGM_CMD_WAIT_12 = 0x7B,
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VGM_CMD_WAIT_13 = 0x7C,
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VGM_CMD_WAIT_14 = 0x7D,
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VGM_CMD_WAIT_15 = 0x7E,
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VGM_CMD_WAIT_16 = 0x7F,
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// Special
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VGM_CMD_END = 0x66, // end of sound data
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};
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// VGM header file data structure
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struct VGM_Header
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{
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// 1.00
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u32 Ident;
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u32 EoF_offset;
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u32 Version;
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u32 SN76489_clock;
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u32 YM2413_clock;
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u32 GD3_offset;
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u32 Total_samples;
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u32 Loop_offset;
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u32 Loop_samples;
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// 1.01
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u32 Rate;
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// 1.10
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u16 SN_FB;
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u8 SNW;
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// 1.51
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u8 SF;
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// 1.10
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u32 YM2612_clock;
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u32 YM2151_clock;
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// 1.50
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u32 Data_offset;
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// 1.51
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u32 Sega_PCM_clock;
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u32 SPCM_Interface;
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u32 RF5C68_clock;
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u32 YM2203_clock;
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u32 YM2608_clock;
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u32 YM2610B_clock;
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u32 YM3812_clock;
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u32 YM3526_clock;
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u32 Y8950_clock;
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u32 YMF262_clock;
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u32 YMF278B_clock;
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u32 YMF271_clock;
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u32 YMZ280B_clock;
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u32 RF5C164_clock;
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u32 PWM_clock;
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u32 AY8910_clock;
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u8 AYT;
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u8 AY_Flags[3];
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// 1.60
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u8 VM;
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u8 dummy7D;
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u8 LB;
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// 1.51
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u8 LM;
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// 1.61
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u32 GB_DMG_clock;
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u32 NES_APU_clock;
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u32 MultiPCM_clock;
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u32 uPD7759_clock;
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u32 OKIM6258_clock;
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u8 OF;
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u8 KF;
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u8 CF;
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u8 dummy97;
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u32 OKIM6295_clock;
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u32 K051649_clock;
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u32 K054539_clock;
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u32 HuC6280_clock;
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u32 C140_clock;
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u32 K053260_clock;
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u32 Pokey_clock;
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u32 QSound_clock;
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// 1.71
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u32 SCSP_clock;
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// 1.70
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u32 Extra_Hdr_ofs;
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// 1.71
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u32 WonderSwan_clock;
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u32 VSU_clock;
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u32 SAA1099_clock;
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u32 ES5503_clock;
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u32 ES5506_clock;
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u16 ES_chns;
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u8 CD;
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u8 dummyD7;
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u32 X1_010_clock;
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u32 C352_clock;
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u32 GA20_clock;
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u32 dummyE4;
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u32 dummyE8;
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u32 dummyEC;
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u32 dummyF0;
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u32 dummyF4;
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u32 dummyF8;
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u32 dummyFC;
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}; |